Modeling MPI Performance on Chip Multiprocessors

Chip Multiprocessors have brought new challenges to MPI programs. A performance bottleneck raises when multiple cores in one chip share hardware resources like last level cache and memory link. The project aims at modeling memory resource sharing effect on verstile MPI applications. The performance model uses the reuse distance and footprint information collected from different MPI tasks to calculate the slowdown from resource sharing and thus to predict the scalability of MPI programs on Chip Multiprocessor based clusters.