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Currently I am working on
- Chip Multiprocessor, Memory Hierarchies, and Cache Coherence Protocols.
Working on protocol enhancements by applying different optimization techniques
such as prediction, migration, and selective replication of data at the L1 cache
level. Using GEMS and SIMICS for performance evaluation.
- Transactional Memory (Software TM and Hardware-Acceleration for STM).
Trying to increase scalability, reduce programming complexity, and overcome the
various semantic problems associated with locks by using TM. Our hardware
acceleration utilizes the underlying cache coherence protocol to achieve
programmable data isolation while allowing flexible conflict detection (eager or
lazy).
In my MSc thesis I have worked on "A General-purpose simulator for Network on Chip (NoC)". NoC is an interconnection network of heterogeneous components such as processors, memories, FPGA, etc. This is a variant of SoC but based on network like communication instead of shared bus approach of SoC. The simulator supports various topologies of the so far developed architectures such as mesh, torus and butterfly-fat-tree. It models the layout of NoC switch supporting wormhole switching as well as investigates the relationship between various parameters such as mesh-size, buffer-size, flit-size, routing decisions, throughput etc.
In my BSc thesis I have worked on "Optimal algorithm for star chromatic number of planar and non-planar graphs". I have developed three new classes of planar and non-planar graphs. I have given the optimal algorithm for coloring those classes of graphs so that star-chromatic number is the minimum and I have showed the correctness of the algorithms.
I did some worke on the problems of Mobile IP specially on handoff latency.
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